LBIST (Logic Built In Self Test) was (and still is) used extensively within IBM on chips to test for both DC and AC faults in the logic and some portions of the arrays. Published materials about LBIST include IBM's TDB v38 n11 of 11-95, dealing with a method an apparatus for handling multiple clock domains within a single logic built-in self test structure. This is but an example of testing during the debug of IBM's system chips. LBIST testing has been used to diagnose and characterize chip problems and uncovered a number of unique failure mechanisms. Two examples of these failure mechanisms are:
1) Coupled noise causing critical signals to change their delay as well as causing latches to change states when certain test patterns were executed.
2) A wide range in process parameters of the chips that were manufactured (for example very strong P-fets with very weak N-fets) stressed some of the dynamic circuits in the arrays, causing intermittent failures.
If these failure mechanisms result in "hard" repeatable faults, LBIST testing could still be used to test the remaining logic since there are known mathematical formulas for determining a new "valid signature" when a "hard" fault exists.
Unfortunately these failure mechanisms resulted in faults that were intermittent and very sensitive to environmental conditions such as power supply and temperature. Hence, LBIST could not be used to test the remaining logic on the chip because we could not determine what the "valid signature" should be. This one intermittent fault could be masking a number of other faults, that may be real design problems, yet LBIST would not be able to test for these faults. This would be desirable.